1. Field of the Invention
The present invention relates to the field of semiconductor devices, and more particularly, to a method of processing a defect source in a wafer edge region.
2. Description of the Related Art
In semiconductor manufacturing, deposited layers from a wafer edge region at various processing stages dislodge contaminant particles, which intrude into a wafer main region where integrated circuit elements are formed, and become a defect source. Accordingly, an edge exposure of wafer (EEW) process is typically carried out to clean the deposited layers of the wafer edge region. The EEW process defines an EEW line at a predetermined region of the wafer edge region between the outermost wafer edge toward the center of the wafer, and etches the deposited layers between the EEW line and the outermost wafer edge (i.e., removes the layers outside of the EEW line). The position of the EEW line varies depending on the process stage when the cleaning occurs. For example, at the stage of storage node contact, bit line contact, and SAC (self-aligned contact) formation processes, the EEW line is defined at the wafer edge region at about 2.0 mm from the outermost of the wafer edge, and at the stage of a capacitor lower electrode formation process, the EEW line is at about 1.5 mm from the wafer edge.
As an integrated circuit memory device becomes highly integrated, integrated circuit elements such as a capacitor become smaller and smaller in size. This results in a decrease in capacitance because the area occupied by the capacitor electrode also decreases. In order to increase the effective area occupied by the capacitor (i.e., to increase capacitance) in a given cell area under recent miniaturization trends of the semiconductor industry, a cylindrical type capacitor storage electrode is being widely employed.
FIG. 1 is a cross-sectional view of a semiconductor wafer showing a rumple surface D of a wafer edge region and particles thereon in the process of manufacturing a cell capacitor storage node, which edge surface D is the focus of the present invention.
Referring to FIG. 1, a source/drain region 112 and a gate electrode 114 are formed on a wafer 110. Contact pads 116 and bit line contact plugs 118 are formed above the source/drain region 112. Bit lines 120 are formed to be electrically connected to contact pads 116 via bit line contact plugs 118. A first insulating layer 124 is formed thereon and storage node contact plugs 122 are formed in the first insulating layer 124 to be electrically connected to contact pads 117. Through a first EEW process, a first EEW line (at distance E2, approximately 2.0 mm from the outermost of the wafer edge) is defined in a wafer edge region (A), and a portion of the first insulating layer outside of the first EEW line is etched away.
A silicon nitride layer 126 is formed on the resultant structure. A sacrificial oxide layer 128 is then formed on the silicon nitride layer 126. A second EEW process is performed. The second EEW process defines a second EEW line (at distance E1, about 1.5 mm from the outermost wafer edge) in the wafer edge region (A). Accordingly, the sacrificial oxide layer 128 and the silicon nitride layer 126 outside of the second EEW line (between the second EEW line and the outermost of the wafer edge) are etched away.
Through a photo-etching process, the sacrificial oxide layer 128 is patterned to form an opening therein, exposing the storage node contact plug 122. Since the topology of sacrificial oxide layer 128 slopes toward the outermost of the wafer edge at the wafer edge region (causing a step at the wafer edge region) due to the first and second EEW processes, a photoresist layer (not shown) is deposited unevenly over the sacrificial oxide layer 128 and is deposited relatively thin at the wafer edge region (A). As a result, during the photo-etching process, the photoresist layer at the step portion of the wafer edge region (A) is also etched away, thereby exposing a region of the sacrificial oxide layer 128. This undesirable etching of the exposed sacrificial oxide layer 128 causes a rumple surface D in the wafer edge region (A).
After removing the photoresist layer, a conductive layer 130 is then formed on the sacrificial oxide layer 128 and within the storage node opening. HSG silicon 134 is formed on the conductive layer 130 as shown. A second insulating layer 136 is formed on the resultant structure. The second insulating layer 136, HSG silicon 134 and the conductive layer 130 are planarized by etching until the sacrificial oxide layer 128 is exposed, to form a cell capacitor storage node. However, residues of HSG silicon 134 and the conductive layer 130 remain on the rumple surface D of the wafer edge region (A). Subsequently, wet etching is carried out to remove the second insulating layer 136 in the storage node opening and the sacrificial oxide layer 128. However, during this wet etching, residues of HSG silicon 134 and the conductive layer 130 may be dislodged from the rumple region to drift freely, thereby becoming a serious source of contamination. Such conductive particles can cause shorts and device failures.
The present invention was made in view of above-mentioned problems and it is an object of the present invention to provide a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication.
It is a feature of the present invention that a photoresist layer pattern is formed to either expose or cover a defect source region at a rumple surface of a wafer edge region. If the defect source is exposed, the exposed defect source is removed from the rumple surface. If the defect source is covered by the photoresist layer pattern, the defect source is fixed in place and is protected by the photoresist layer pattern during a wet cleaning process, thereby preventing the defect source from dislodging to drift freely into a wafer main region.
In accordance with the present invention, there is provided a method of eliminating or covering a defect source in a wafer edge region, the wafer being defined by the wafer edge region and a wafer main region. The method includes forming an insulating layer on a surface of the wafer. The insulating layer in the wafer edge region is damaged during a subsequent process, and conductive contaminants undesirably remain thereat during subsequent deposition of a conductive layer and planarizing processes. A photoresist layer is formed on the resultant structure having the conductive contaminants. The photoresist layer is then patterned to expose either the wafer edge region or the wafer main region.
The wafer edge region is defined as a ring shaped region with a predetermined width from the outermost part of the wafer edge where integrated circuit elements normally operating do not exist.
In accordance with the present invention, there is provided a method of processing a defect source in a wafer edge region. The method includes forming a first insulating layer on the wafer. An edge exposure of wafer (EEW) line is defined at a predetermined region of the wafer edge region and the first insulating layer outside of the EEW line is removed. Namely, the first insulating layer between the EEW line and the outermost part of the wafer edge is removed. The first insulating layer is patterned to form an opening therein in the wafer main region. A conductive layer is formed on an entire surface of the wafer including the opening. A second insulating layer is formed on the resultant structure having the opening. A photoresist layer is formed on the second insulating layer. A selected part of the photoresist layer in the wafer edge region is removed through an EEW process. An EEW line for removing the photoresist layer is at the wafer edge region nearer to the wafer main region than the EEW line for removing the first insulating layer. The exposed second insulating layer in the wafer edge region by the remnant photoresist layer is etched to expose the conductive layer. The remnant photoresist layer is removed. The exposed conductive layer in the wafer edge region is removed by using the second insulating layer as an etching mask. The second insulating layer and the conductive layer in the wafer main region are planarized until the first insulating layer is exposed.
Preferably, HSG silicon is formed on the conductive layer. The EEW line for removing the first insulating layer is formed at the wafer edge region of about 1.5 mm from the outermost part of the wafer. The EEW line for the removing the photoresist layer is formed at the wafer edge region of about 3.0 mm from the outermost part of the wafer.
In accordance with the present invention, there is provided a method of processing a defect source at a wafer edge region in a semiconductor manufacturing, the wafer being defined by the wafer edge region and a wafer main region. The method includes forming a first insulating layer on the wafer having transistors, bit lines, and contact plugs. An EEW line is defined at the wafer edge region from an outermost part of the wafer edge. The first insulating layer outside of the EEW line is removed. A first photoresist pattern is formed on an entire surface of the wafer. The first insulating layer is patterned to form opening for a storage node therein in the wafer main region by using the first photoresist pattern as an etching mask. The first photoresist pattern is removed. A conductive layer is formed on resultant structure having the opening. A second insulating layer is formed on the conductive layer. The second insulating layer and the conductive layer are planarized until the first insulating layer is exposed. A second photoresist layer is formed over the resultant structure. Another EEW line is defined at the wafer edge region and the second photoresist layer inside of the another EEW line is removed. Namely, the second photoresist layer in the wafer main region.
The wafer edge region is a ring shaped region with a predetermined width from the outermost part of the wafer edge at which integrated circuit elements normally operating do not exist.
Preferably, the EEW line for removing the first insulating layer is formed at the wafer edge region of about 1.5 mm from the outermost part of the wafer edge. The another EEW line for removing the second photoresist layer is formed nearer to the wafer main region than the EEW line for removing the first insulating layer. The another EEW line for removing the second photoresist layer is formed at the wafer edge region of approximately 3.0 mm from the outermost part of the wafer. The conductive layer is made of a conductive material that has an etching selectivity of at least 5:1 with respect to the first and second insulating layer.